Global Unichip Announces +3X Schedule Reduction of Full-Chip Design Closure on 50M Gate Design with New Encounter Digital Implementation System

Silicon Predictability, Complete Multi-Mode/Multi-Corner Analysis, and Embedded Timing Signoff and Signal Integrity Drive Rapid Design Closure

SAN JOSE, CA, April 2, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Global Unichip Corporation (GUC) successfully taped out a 65-nanometer, high-performance networking switch processor that features 50 million gates and an operating speed of 400 megahertz. GUC designed the large, complex chip using the Cadence® Encounter® Digital Implementation System to achieve a significant reduction in overall chip design time.

"Our ability to successfully tapeout this high-performance, high gate-count design using the Encounter Digital Implementation System reinforces Global Unichip's leadership in managing large and complex designs," said Chi-Chiang Hsieh, VP of Global Unichip. "It also exemplifies the productivity-improving capabilities of the Encounter Digital Implementation System, which allowed us to achieve full chip-design closure in one week, as opposed to one month using a traditional approach."

These improvements were made possible through the Encounter Digital Implementation System's top-level design planning-and-assembly, highly predictable block timing closure flow and end-to-end multi-processing capabilities, including superthreaded routing. In addition, by adopting top-down timing budgeting and virtual flat methodology using dynamic timing modeling technology in this hierarchical design, GUC achieved good block level implementation quality, enabling chip integration success in one single iteration.

The 65nm, ultra-high performance network switch processor is capable of transmitting at 3GHz and includes a 10 Gigabit Attachment Unit Interface (XAUI) for high-speed interoperability. The 50 million gate design was partitioned into 18 blocks, the largest partition having 12 million gates. Since the turnaround time including chip level prototyping and budgeting/partition could be done within one day, designers could focus on solving design issues instead of being concerned with the tool's run time. The early timing, area and congestion estimations with minimal user intervention enabled GUC to complete the floorplan in a faster and more predictable manner.

In order to handle seven process corners and two distinct constraint modes in block level implementation, GUC turned to Encounter Digital Implementation System's high capacity block timing closure flow, which uses a streamlined software architecture to achieve reduced runtime on end-to-end block implementation while meeting aggressive timing performance requirements. In addition, GUC leveraged Cadence NanoRoute® Router's superthreading capabilities to drastically reduce routing runtime on this design. The integrated Encounter Timing System signoff capabilities in the Encounter Digital Implementation System resulted in fewer iterations between implementation and signoff and more predictable convergence.

"The successful tapeout of this complex chip demonstrates the Cadence commitment to providing robust solutions that deliver faster design closure," said Chi-Ping Hsu, senior vice president of research and development for the Implementation Products Group at Cadence. "The enhanced end-to-end multi-processing capabilities and integrated timing signoff have helped many customers overcome the complexities of implementing large, high-performance designs. Global Unichip's tapeout is a testament to the leading capabilities of the new Encounter Digital Implementation System."

Source: Cadence Design Systems, Inc.